Design a 4GHz PLL for wireless receiver

Abstract

:This paper presents the design of a 4 GHz PLL used in wireless receiver. The Verilog-A models are used in behavioral level simulation and in post-layout simulation. The design is based on SMIC 0.18 um 1P6M CMOS RF process. The settling time is 19us and the reference spur is 42.2 dB, the phase noise of VCO is -115 dBc/Hz@lMHz, the power dissipation of the PLL is 36 mW.