Decomposition of multi-output functions for CPLDs

Abstract

A paper presents decomposition method dedicated for PAL based CPLDs. Non-standard usage of decomposition, that leads to minimization of area in implemented circuit and reduction of used logic blocks in programmable structure is the aim of proposed method. Each decomposition step (bound set selection, graph colouring, column pattern coding, etc) is oriented for implementation in PAL-based structure that characterized by PAL-based logic block. Proposed decomposition method is an extension of classical approach commonly thought to be sufficiently efficient. Experiments that were carried out on typical benchmarks show significant area reduction.