Automatic generation of functional coverage models from CTL

2007 IEEE International High Level Design Validation and Test Workshop Pub Date : 2007-11-07 DOI:10.1109/HLDVT.2007.4392806

Shireesh Verma, I. Harris, Kiran Ramineni

引用次数: 10

Abstract

Functional coverage models which measure the sufficiency of test stimuli are essential to the verification process. A key source of difficulty in their deployment emanates from the manual and imprecise nature of their development process and the lack of a sound measure of their quality. A functional coverage model can be considered complete only if it accurately reflects the behavior of the Design under Verification (DUV) as described in the specification. We present a method to automatically generate coverage models from a formal CTL description of design properties. Experimental results show that the functional coverage models generated using our technique correlate well with the detection of randomly injected errors into a design.

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

从 CTL 自动生成功能覆盖模型

衡量测试刺激是否充分的功能覆盖模型对验证过程至关重要。部署这些模型的一个主要困难来源于其开发过程的手工和不精确性，以及缺乏对其质量的合理衡量。只有当功能覆盖模型能准确反映规范中描述的被验证设计（DUV）的行为时，它才能被认为是完整的。我们介绍了一种从设计属性的正式 CTL 描述自动生成覆盖模型的方法。实验结果表明，使用我们的技术生成的功能覆盖模型与设计中随机注入错误的检测结果有很好的相关性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文去求助

来源期刊

2007 IEEE International High Level Design Validation and Test Workshop

自引率

0.00%

发文量

期刊最新文献

Reliable network-on-chip based on generalized de Bruijn graph Automatic error diagnosis and correction for RTL designs A novel formal approach to generate high-level test vectors without ILP and SAT solvers Hierarchical cache coherence protocol verification one level at a time through assume guarantee Towards RTL test generation from SystemC TLM specifications