A logic synthesis system for VHDL design descriptions

Abstract

The VHSIC hardware description language (VHDL) is emerging as an industry standard for the modeling of electronic systems. A description is given of a logic synthesis system developed to realize ASIC CMOS chip designs from VHDL descriptions, designs optimized for cell count and performance. The utilization of VHDL attributes and the interpretation of attribute data by synthesis transformations are highlighted. Timing optimization algorithms based upon calculated timing slack values are described in detail. The unique means by which clock repowering trees are incorporated is also discussed.<>