Pub Date : 1989-12-01DOI: 10.1109/ICCAD.1989.76982
K. Roy, J. Abraham, K. De, S. Lusky
The synthesis of combinational logic which is robust delay fault testable is developed. In a circuit, any reconvergent fanout may result in the presence of blocked paths and/or paths which can be sensitized only if some other path is also sensitized. Implicit don't care terms are used to detect these problems and a local transformation at the reconvergence point is used to upgrade the delay fault testability of the circuit. The sharing of terms in a multilevel circuit is preserved to the greatest extent possible. Good results have been obtained based on an implementation of the algorithm in the LISP programming language on a TI Explorer machine.<>
{"title":"Synthesis of delay fault testable combinational logic","authors":"K. Roy, J. Abraham, K. De, S. Lusky","doi":"10.1109/ICCAD.1989.76982","DOIUrl":"https://doi.org/10.1109/ICCAD.1989.76982","url":null,"abstract":"The synthesis of combinational logic which is robust delay fault testable is developed. In a circuit, any reconvergent fanout may result in the presence of blocked paths and/or paths which can be sensitized only if some other path is also sensitized. Implicit don't care terms are used to detect these problems and a local transformation at the reconvergence point is used to upgrade the delay fault testability of the circuit. The sharing of terms in a multilevel circuit is preserved to the greatest extent possible. Good results have been obtained based on an implementation of the algorithm in the LISP programming language on a TI Explorer machine.<<ETX>>","PeriodicalId":394675,"journal":{"name":"1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127408600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-12-01DOI: 10.1109/ICCAD.1989.77001
R. Mueller-Thuns, D. Saab, R. Damiano, J. Abraham
Consideration is given to the use of general-purpose multiprocessors for various simulation tasks. The aims of the work are to define a general framework for the parallel simulation of digital systems and to develop and evaluate tools for logic and fault simulation that have a good cost-performance ratio. Specifically, a novel partitioning approach is introduced and used as the basis for the parallel logic and fault simulation of synchronous gate-level designs. Performance experiments with prototype implementations on a message passing and a shared memory machine give promising results, in particular for fault simulation.<>
{"title":"Portable parallel logic and fault simulation","authors":"R. Mueller-Thuns, D. Saab, R. Damiano, J. Abraham","doi":"10.1109/ICCAD.1989.77001","DOIUrl":"https://doi.org/10.1109/ICCAD.1989.77001","url":null,"abstract":"Consideration is given to the use of general-purpose multiprocessors for various simulation tasks. The aims of the work are to define a general framework for the parallel simulation of digital systems and to develop and evaluate tools for logic and fault simulation that have a good cost-performance ratio. Specifically, a novel partitioning approach is introduced and used as the basis for the parallel logic and fault simulation of synchronous gate-level designs. Performance experiments with prototype implementations on a message passing and a shared memory machine give promising results, in particular for fault simulation.<<ETX>>","PeriodicalId":394675,"journal":{"name":"1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127570186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-11-05DOI: 10.1109/ICCAD.1989.77013
M. Abadir
An overview is given of a knowledge-based testability insertion guidance expert system (TIGER) that provides designers with a systematic approach for creating complex, testable designs. Specifically, this system identifies testability problems early in the design cycle, formulates a test strategy for the design, does 'what-if' exploration of DFT (design for testability) solutions, plans the invocation of gate-level test tools on design partitions, and develops a low-cost solution to the test problem that satisfies the design goals and constraints. Also described are the experimental results obtained using the system on several real designs.<>
{"title":"TIGER: testability insertion guidance expert system","authors":"M. Abadir","doi":"10.1109/ICCAD.1989.77013","DOIUrl":"https://doi.org/10.1109/ICCAD.1989.77013","url":null,"abstract":"An overview is given of a knowledge-based testability insertion guidance expert system (TIGER) that provides designers with a systematic approach for creating complex, testable designs. Specifically, this system identifies testability problems early in the design cycle, formulates a test strategy for the design, does 'what-if' exploration of DFT (design for testability) solutions, plans the invocation of gate-level test tools on design partitions, and develops a low-cost solution to the test problem that satisfies the design goals and constraints. Also described are the experimental results obtained using the system on several real designs.<<ETX>>","PeriodicalId":394675,"journal":{"name":"1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123587553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-11-05DOI: 10.1109/ICCAD.1989.76959
G. Colón-Bonet, E. Schwarz, D. Bostick, G. Hachtel, M. Lightner
The authors describe efficient polynomial algorithms for the extraction of topologically minimal multilevel Boolean equations and don't care conditions from the C-based hardware description language CHDL, which has control constructs switch, if-then-else, and go-to. They show that significant savings in CPU cost, area cost, and robustness may be obtained by applying these algorithms as a preprocessing step before using higher cost minimization tools such as BOLD or misII. The approach is based on a control-flow-graph construct with embedded set-use-graph information. The algorithms parse a CHDL description into a directed, nonseries parallel control flow graph. In cases where the graph is also acyclic, graph search and decomposition algorithms are used to derive a Boolean network representing the implied combinational logic. The derived equations are topologically irredundant in the sense that the topological identities are associated with the fork, and join nodes of the control flow graph are accounted for in the code generation. Without this feature, multilevel logic optimizers would have to flatten the control expressions down to primary inputs to discover these identities.<>
{"title":"On optimal extraction of combinational logic and don't care sets from hardware description languages","authors":"G. Colón-Bonet, E. Schwarz, D. Bostick, G. Hachtel, M. Lightner","doi":"10.1109/ICCAD.1989.76959","DOIUrl":"https://doi.org/10.1109/ICCAD.1989.76959","url":null,"abstract":"The authors describe efficient polynomial algorithms for the extraction of topologically minimal multilevel Boolean equations and don't care conditions from the C-based hardware description language CHDL, which has control constructs switch, if-then-else, and go-to. They show that significant savings in CPU cost, area cost, and robustness may be obtained by applying these algorithms as a preprocessing step before using higher cost minimization tools such as BOLD or misII. The approach is based on a control-flow-graph construct with embedded set-use-graph information. The algorithms parse a CHDL description into a directed, nonseries parallel control flow graph. In cases where the graph is also acyclic, graph search and decomposition algorithms are used to derive a Boolean network representing the implied combinational logic. The derived equations are topologically irredundant in the sense that the topological identities are associated with the fork, and join nodes of the control flow graph are accounted for in the code generation. Without this feature, multilevel logic optimizers would have to flatten the control expressions down to primary inputs to discover these identities.<<ETX>>","PeriodicalId":394675,"journal":{"name":"1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122716976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-11-05DOI: 10.1109/ICCAD.1989.76894
A. Mirzaian
The single-layer rectilinear river routing model with no restriction on the number of jogs per wire is considered. In particular, the author studies the model in which there is a fixed constant upper bound J on the number of jogs each wire can have. The author proposes an optimal O(n) time algorithm for the feasibility problem. This leads to an O(n log n) time algorithm for the minimum separation problem. Both algorithms take O(n) space are quite practical. This is a significant improvement over T.C. Tuan and S.L. Hakimi's (1987) minimum separation algorithm, which is designed for J=2 and takes O(n/sup 3/) time and O(n/sup 2/) space.<>
{"title":"A minimum separation algorithm for river routing with bounded number of jogs","authors":"A. Mirzaian","doi":"10.1109/ICCAD.1989.76894","DOIUrl":"https://doi.org/10.1109/ICCAD.1989.76894","url":null,"abstract":"The single-layer rectilinear river routing model with no restriction on the number of jogs per wire is considered. In particular, the author studies the model in which there is a fixed constant upper bound J on the number of jogs each wire can have. The author proposes an optimal O(n) time algorithm for the feasibility problem. This leads to an O(n log n) time algorithm for the minimum separation problem. Both algorithms take O(n) space are quite practical. This is a significant improvement over T.C. Tuan and S.L. Hakimi's (1987) minimum separation algorithm, which is designed for J=2 and takes O(n/sup 3/) time and O(n/sup 2/) space.<<ETX>>","PeriodicalId":394675,"journal":{"name":"1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121354193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-11-05DOI: 10.1109/ICCAD.1989.76930
R. D. Acosta, Steven P. Smith, J. Larson
The VHSIC hardware description language (VHDL) supports the hierarchical design, documentation, and simulation of a wide range of digital system abstractions. VHDL, however, is often cited as difficult to use and inefficient for simulating designs below the gate level. The authors present the mixed-mode simulation facilities of a VHDL system that overcome this limitation by effectively merging gate and switch primitive evaluation routines with VHDL processes. A high-performance mixed-mode simulation capability is achieved through integrated approaches to interface compilation, data structuring, and implementation of the simulation cycle. Several experimental results serve as preliminary justification for this methodology.<>
{"title":"Mixed-mode simulation of compiled VHDL programs","authors":"R. D. Acosta, Steven P. Smith, J. Larson","doi":"10.1109/ICCAD.1989.76930","DOIUrl":"https://doi.org/10.1109/ICCAD.1989.76930","url":null,"abstract":"The VHSIC hardware description language (VHDL) supports the hierarchical design, documentation, and simulation of a wide range of digital system abstractions. VHDL, however, is often cited as difficult to use and inefficient for simulating designs below the gate level. The authors present the mixed-mode simulation facilities of a VHDL system that overcome this limitation by effectively merging gate and switch primitive evaluation routines with VHDL processes. A high-performance mixed-mode simulation capability is achieved through integrated approaches to interface compilation, data structuring, and implementation of the simulation cycle. Several experimental results serve as preliminary justification for this methodology.<<ETX>>","PeriodicalId":394675,"journal":{"name":"1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121668313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-11-05DOI: 10.1109/ICCAD.1989.76939
P. Ashar, S. Devadas, A. Newton
The authors formulate the problem of optimum two-way finite-sole-machine (FSM) decomposition as one of symbolic-output partitioning and show that this is an easier problem than optimum state assignment. They describe a procedure of constrained prime-implicant generation and covering that represents an optimum FSM decomposition algorithm under the specified cost function. Exact procedures are not viable for large problem instances. The authors give a novel iterative optimization strategy of symbolic-implicant expansion and reduction, modified from two-level Boolean minimizers, that represents a heuristic algorithm based on their exact procedure. Reduction and expansion are performed on functions with symbolic, rather than binary-valued, outputs. Preliminary experimental results that illustrate both the efficacy of the proposed algorithms and the validity of the selected cost function.<>
{"title":"Optimum and heuristic algorithms for finite state machine decomposition and partitioning","authors":"P. Ashar, S. Devadas, A. Newton","doi":"10.1109/ICCAD.1989.76939","DOIUrl":"https://doi.org/10.1109/ICCAD.1989.76939","url":null,"abstract":"The authors formulate the problem of optimum two-way finite-sole-machine (FSM) decomposition as one of symbolic-output partitioning and show that this is an easier problem than optimum state assignment. They describe a procedure of constrained prime-implicant generation and covering that represents an optimum FSM decomposition algorithm under the specified cost function. Exact procedures are not viable for large problem instances. The authors give a novel iterative optimization strategy of symbolic-implicant expansion and reduction, modified from two-level Boolean minimizers, that represents a heuristic algorithm based on their exact procedure. Reduction and expansion are performed on functions with symbolic, rather than binary-valued, outputs. Preliminary experimental results that illustrate both the efficacy of the proposed algorithms and the validity of the selected cost function.<<ETX>>","PeriodicalId":394675,"journal":{"name":"1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"73 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132477155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-11-05DOI: 10.1109/ICCAD.1989.77006
J. Janak, D. D. Ling, H. Huang
A description is given of C3DSTAR, a capacitance program for three-dimensional configurations of conductors and dielectrics, that incorporates a hybrid integral-equation solution of the capacitance problem. The hybrid method combines the use of multilayer Green's function treatment of the infinite planar dielectric interfaces with an explicit treatment of the bound charge at finite and/or irregular dielectric interfaces. The approach described differs from previous hybrid integral equation methods in that the free charge density is the primary unknown, rather than the total charge density. This allows early elimination of numerically induced asymmetry in the capacitance matrix and results in more accurate capacitive values.<>
{"title":"C3DSTAR: a 3D wiring capacitance calculator","authors":"J. Janak, D. D. Ling, H. Huang","doi":"10.1109/ICCAD.1989.77006","DOIUrl":"https://doi.org/10.1109/ICCAD.1989.77006","url":null,"abstract":"A description is given of C3DSTAR, a capacitance program for three-dimensional configurations of conductors and dielectrics, that incorporates a hybrid integral-equation solution of the capacitance problem. The hybrid method combines the use of multilayer Green's function treatment of the infinite planar dielectric interfaces with an explicit treatment of the bound charge at finite and/or irregular dielectric interfaces. The approach described differs from previous hybrid integral equation methods in that the free charge density is the primary unknown, rather than the total charge density. This allows early elimination of numerically induced asymmetry in the capacitance matrix and results in more accurate capacitive values.<<ETX>>","PeriodicalId":394675,"journal":{"name":"1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"47 20","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131805152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-11-05DOI: 10.1109/ICCAD.1989.76972
P. Rankin, J. Siemensma
A general-purpose optimization engine is described which can exploit the extensive circuit parameterization, macromodeling, and analysis features of a mature circuit simulator and can easily be coupled to new optimization algorithms. This engine is couched in a novel interactive environment which integrates the manual design cycle of modification and simulation with automatic circuit improvement. Complicated performance requirements can be specified graphically, design variables easily identified, and an algorithm selected for optimization. the optimizer's progress can be replayed, comparing circuit performance against specifications.<>
{"title":"Analogue circuit optimization in a graphical environment","authors":"P. Rankin, J. Siemensma","doi":"10.1109/ICCAD.1989.76972","DOIUrl":"https://doi.org/10.1109/ICCAD.1989.76972","url":null,"abstract":"A general-purpose optimization engine is described which can exploit the extensive circuit parameterization, macromodeling, and analysis features of a mature circuit simulator and can easily be coupled to new optimization algorithms. This engine is couched in a novel interactive environment which integrates the manual design cycle of modification and simulation with automatic circuit improvement. Complicated performance requirements can be specified graphically, design variables easily identified, and an algorithm selected for optimization. the optimizer's progress can be replayed, comparing circuit performance against specifications.<<ETX>>","PeriodicalId":394675,"journal":{"name":"1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"22 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130884969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-11-05DOI: 10.1109/ICCAD.1989.76993
Hyoung B. Min, W. A. Rogers, Hwei-Tsu Ann Luh
FANHAT, has been designed and implemented to accelerate test generation for digital circuits. FANHAT uses a minimal hierarchical representation of the circuit and functional level heuristics to perform implication, propagation, and backtracking with high-level functional model. Experiments with three circuits show hierarchical test generation using FANHAT is 1.5 to 8.9 times faster than flat gate-level test generation.<>
{"title":"FANHAT: fanout oriented hierarchical automatic test generation system","authors":"Hyoung B. Min, W. A. Rogers, Hwei-Tsu Ann Luh","doi":"10.1109/ICCAD.1989.76993","DOIUrl":"https://doi.org/10.1109/ICCAD.1989.76993","url":null,"abstract":"FANHAT, has been designed and implemented to accelerate test generation for digital circuits. FANHAT uses a minimal hierarchical representation of the circuit and functional level heuristics to perform implication, propagation, and backtracking with high-level functional model. Experiments with three circuits show hierarchical test generation using FANHAT is 1.5 to 8.9 times faster than flat gate-level test generation.<<ETX>>","PeriodicalId":394675,"journal":{"name":"1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133676108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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