{"title":"A low-power graphics LSI integrating 29Mb embedded DRAM for mobile multimedia applications","authors":"Ramchan Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun Song, Young-Don Bae, H. Yoo","doi":"10.1109/ASPDAC.2004.1337635","DOIUrl":null,"url":null,"abstract":"A low-power graphics LSI is designed and implemented for mobile multimedia applications. The LSI contains a 32bit RISC processor with enhanced MAC, a 3D rendering engine, programmable power optimizer, and 29Mh embedded DRAM. Full 3D graphics pipeline featuring 264Mtexelds texture-mapped 3D graphics as well as 2D MPEG-4 video decoding can be realized while consuming less than 210mW and 12lmm2 chip area. The chip is implemented with 0.16μm pure DRAM process to reduce the fabrication cost. The real-time 3D graphics applications are successfully demonstrated by the fabricated chip on two PDA system boards.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASPDAC.2004.1337635","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
A low-power graphics LSI is designed and implemented for mobile multimedia applications. The LSI contains a 32bit RISC processor with enhanced MAC, a 3D rendering engine, programmable power optimizer, and 29Mh embedded DRAM. Full 3D graphics pipeline featuring 264Mtexelds texture-mapped 3D graphics as well as 2D MPEG-4 video decoding can be realized while consuming less than 210mW and 12lmm2 chip area. The chip is implemented with 0.16μm pure DRAM process to reduce the fabrication cost. The real-time 3D graphics applications are successfully demonstrated by the fabricated chip on two PDA system boards.
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