A methodology for wafer scale integration of linear pipelined arrays

Abstract

A methodology for designing large one-dimensional pipelined array processing architectures where a large number of defects can be expected is presented. Central to the methodology is a functional separation at each processing element between the processing core and the inter-cell communication path. Using an 'interconnection harness' which provides the inter-cell communication medium and straps or links the underlying processing cores into a working array, 100% utilisation of the 'healthy' processing elements can be achieved. The harness which snakes across the wafer and forms the backbone of this architecture is made highly reliable and capable of sustaining up to a maximum of N single errors in an N cell array.<>