Optimization of hot carrier resistance for 0.18µm CMOS technology

Abstract

With the further scaling down of CMOS devices, hot carrier induced degradation has become one of the most important reliability concerns. In the hot carrier effect, carriers are accelerated by the channel electric fields and become trapped in the oxide. These trapped charges cause time dependent shifts in measured device parameters. In time, substantial device parameter degradation can occur, resulting in device failure. Studies have been carried out to enhance device hot carrier immunity by reducing and departure the high electrical field from the drain area. The evaluations were focused on the implant energy and dose factors in order to achieve more graded device junction. The substantial result shows 10 times improvement in hot carrier injection (HCI) DC lifetime and reveals a good direction for suppression the hot carrier effects in 0.18 μm CMOS technology.