H. V. Le, H. T. Duong, C. Ta, A. Huynh, Robin J. Evans, E. Skafidas
{"title":"A 77 GHz CMOS low noise amplifier for automotive radar receiver","authors":"H. V. Le, H. T. Duong, C. Ta, A. Huynh, Robin J. Evans, E. Skafidas","doi":"10.1109/RFIT.2012.6401651","DOIUrl":null,"url":null,"abstract":"This paper presents the design of a low noise amplifier (LNA) for automotive radar application operating at 76-77 GHz. The LNA consists of 5 cascade common source amplifiers. The output of each stage is positioned close to the gate of the next stage creating a LC resonance output load, therefore complex interstage matching networks are eliminated. Moreover, transmission lines (T Ls) are utilized to create matching and load inductors. As a result, chip size is significantly reduced. The proposed LNA is implemented in a 65 nm CMOS technology and measurement results show 11 dB voltage gain, and 7.8 dB noise figure (NF) while dissipating 21.5 mA from 1.2 V supply.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIT.2012.6401651","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 20
Abstract
This paper presents the design of a low noise amplifier (LNA) for automotive radar application operating at 76-77 GHz. The LNA consists of 5 cascade common source amplifiers. The output of each stage is positioned close to the gate of the next stage creating a LC resonance output load, therefore complex interstage matching networks are eliminated. Moreover, transmission lines (T Ls) are utilized to create matching and load inductors. As a result, chip size is significantly reduced. The proposed LNA is implemented in a 65 nm CMOS technology and measurement results show 11 dB voltage gain, and 7.8 dB noise figure (NF) while dissipating 21.5 mA from 1.2 V supply.
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