Modeling and analysis of III–V logic FETs for devices and circuits: Sub-22nm technology III–V SRAM cell design

Abstract

A compact model of III–V HFETs is developed for digital logic circuit applications such as a 6T-SRAM cell. We study sub-22nm technology III–V SRAM circuit design via III–V MOSFETs with thin high-k dielectric for low gate tunneling current, and optimized extrinsic structure for minimum parasitic capacitance. We investigate the drawbacks of a weak PMOS device in a SRAM cell and propose a minimum requirement for III–V PMOS strength for SRAM to be viable.