Design of radix 4 divider circuit using SRT algorithm

Abstract

The arithmetic operations are widely used in calculators and digital system. High speed methods of calculating are currently being requested, hence the design of fast divider is an important issues in high speed computing. In this paper we present fast radix-4 SRT division architecture with the digit-recurrent approach in which the quotient is obtained one digit per iteration. In this we estimating quotient digit instead of finding the exact one. The speculated quotient digit is used to calculate two possible partial remainders, in parallel with updating the new partial remainder for the next step whiles the quotient digit is being corrected. The two step processes does not affect the division speed, the approach has fast speed performance due to significant reduction in table size and by using higher radix, proposed divider takes power of 32.92μw with delay of 1.18 ns with 0.18μm CMOS technology.