Enhancing ESys.Net with a semi-formal verification layer

Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004. Pub Date : 2004-12-06 DOI:10.1109/ICM.2004.1434594

N. Gorse, M. Metzger, J. Lapalme, E. Aboulhamid, Y. Savarie, G. Nicolescu

引用次数: 4

Abstract

As electronic systems reach tremendous complexity, new CAD tools are needed to cope with their design and verification. ESys.Net, a new design environment under development at Universite de Montreal proposes an elegant solution for modeling and simulation. This paper presents the extension of this environment with a complete verification layer based on linear temporal logic. This is a major enhancement to ESys.Net, since it allows designers to use it not only for modeling and simulation but also for verification.

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加强ESys。带有半正式验证层的

随着电子系统越来越复杂，需要新的CAD工具来处理它们的设计和验证。ESys。Net是蒙特利尔大学正在开发的一个新的设计环境，它为建模和仿真提供了一个优雅的解决方案。本文提出了基于线性时间逻辑的完整验证层对该环境的扩展。这是对ESys的主要改进。Net，因为它允许设计人员不仅使用它进行建模和仿真，还可以进行验证。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.

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