Clock Optimization Techniques

Abstract

In the ASIC design convergence, the clock tree synthesis is one of the critical phase. A good quality of clock tree synthesis will ensure easier timing convergence during post route phase. During design convergence phase, users may need to have multiple re-spins on placement optimization, clock tree optimization before proceeding to post route optimization with decent timing quality, for high performance blocks. This process may consume 50% of backend design cycle, to ensure a decent turn around time and acceptable timing results from post route optimization, before proceeding to timing engineering change order (ECO). The objective of this paper, is to share the clock tree optimization techniques and the result of the optimization techniques, from timing, power and skew aspects. Hopefully, the finding will benefit the design community in clock optimization solutions.