{"title":"A 6-digit RSD analog-to-quaternary converter with CMOS Current Mode Quaternary Adders","authors":"C. Chan, C. Chan, C. Choy, K. Pun","doi":"10.1109/ICASIC.2007.4415623","DOIUrl":null,"url":null,"abstract":"This paper presents a 6-digit Analog-to-Quaternary Converter (AQC) using a 0.35 mum CMOS process. The proposed CMOS AQC uses pipelined architecture with redundant signed digit (RSD) error correction algorithm. A CMOS quaternary adder is proposed to handle quaternary addition in the correction algorithm. The converter has simulated SNDR SFDR and THD of 65.17 dB, 73.89d B and -73.26 dB at 2.5V supply voltage and 50 MHz sampling rate.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 7th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASIC.2007.4415623","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper presents a 6-digit Analog-to-Quaternary Converter (AQC) using a 0.35 mum CMOS process. The proposed CMOS AQC uses pipelined architecture with redundant signed digit (RSD) error correction algorithm. A CMOS quaternary adder is proposed to handle quaternary addition in the correction algorithm. The converter has simulated SNDR SFDR and THD of 65.17 dB, 73.89d B and -73.26 dB at 2.5V supply voltage and 50 MHz sampling rate.
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