PRUS - processor network for digital circuit implementation

Stanley Hyduke, V. Hahanov, V. Obrizan, O. Guz
{"title":"PRUS - processor network for digital circuit implementation","authors":"Stanley Hyduke, V. Hahanov, V. Obrizan, O. Guz","doi":"10.1109/DSD.2005.65","DOIUrl":null,"url":null,"abstract":"This paper offers high-performance technology for processing Boolean equations, based on compiler synchronized parallel-processor network-based logic device PRUS (programmable unlimited systems) - single-bit spherical multiprocessor, implemented into ASIC. This technology allows to perform parallel, sequential and pipelined Boolean equations processing using AND, OR, NOT, XOR operations. Multiprocessor is very efficient in hardware implementation - e.g. 256MB RAM is enough for processing Boolean equations containing 20 millions gates.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"8th Euromicro Conference on Digital System Design (DSD'05)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DSD.2005.65","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

This paper offers high-performance technology for processing Boolean equations, based on compiler synchronized parallel-processor network-based logic device PRUS (programmable unlimited systems) - single-bit spherical multiprocessor, implemented into ASIC. This technology allows to perform parallel, sequential and pipelined Boolean equations processing using AND, OR, NOT, XOR operations. Multiprocessor is very efficient in hardware implementation - e.g. 256MB RAM is enough for processing Boolean equations containing 20 millions gates.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
用于数字电路实现的处理器网络
本文提出了一种基于编译同步并行处理器网络的逻辑器件PRUS(可编程无限系统)的高性能布尔方程处理技术,并将其实现在ASIC中。该技术允许使用and, OR, NOT, XOR操作执行并行,顺序和流水线布尔方程处理。多处理器在硬件实现上非常高效——例如,256MB的RAM足以处理包含2000万个门的布尔方程。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
A processor for testing mixed-signal cores in system-on-chip Educational tool for the demonstration of DfT principles based on scan methodologies Capturing processor architectures from protocol processing applications: a case study Power-composition profile driven co-synthesis with power management selection for dynamic and leakage energy reduction High-level synthesis in latency insensitive system methodology
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1