{"title":"A digital phase-based on-fly offset compensation method for decision feedback equalisers","authors":"Andres Amaya, Javier Ardila, Elkim Roa","doi":"10.1049/cds2.12027","DOIUrl":null,"url":null,"abstract":"<p>A low-complexity method to reduce the offset voltage of dynamic comparators employed as samplers in decision feedback equalisers (DFE) is introduced. The authors propose the phase-domain offset reduction technique (PORT), which leverages an all-digital phase estimation of output data for offset compensation, without setting the comparator input to a common-mode voltage (<b><i>V</i></b><sub><b><i>CM</i></b></sub>). While traditional techniques might break the data link for offset adjustment, the proposed technique allows calibrating the comparator on-the-fly. Measurements from a 26-dB-loss on-chip emulated channel with chip-scope capability validates PORT through eye-diagrams at sampler input. A prototype was implemented in a TSMC 130 nm 1.2 V process, and experimental results show the possibility of extending PORT to state-of-the-art technology nodes for multi-gigabit operation.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":null,"pages":null},"PeriodicalIF":1.0000,"publicationDate":"2021-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12027","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Iet Circuits Devices & Systems","FirstCategoryId":"5","ListUrlMain":"https://onlinelibrary.wiley.com/doi/10.1049/cds2.12027","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
A low-complexity method to reduce the offset voltage of dynamic comparators employed as samplers in decision feedback equalisers (DFE) is introduced. The authors propose the phase-domain offset reduction technique (PORT), which leverages an all-digital phase estimation of output data for offset compensation, without setting the comparator input to a common-mode voltage (VCM). While traditional techniques might break the data link for offset adjustment, the proposed technique allows calibrating the comparator on-the-fly. Measurements from a 26-dB-loss on-chip emulated channel with chip-scope capability validates PORT through eye-diagrams at sampler input. A prototype was implemented in a TSMC 130 nm 1.2 V process, and experimental results show the possibility of extending PORT to state-of-the-art technology nodes for multi-gigabit operation.
期刊介绍:
IET Circuits, Devices & Systems covers the following topics:
Circuit theory and design, circuit analysis and simulation, computer aided design
Filters (analogue and switched capacitor)
Circuit implementations, cells and architectures for integration including VLSI
Testability, fault tolerant design, minimisation of circuits and CAD for VLSI
Novel or improved electronic devices for both traditional and emerging technologies including nanoelectronics and MEMs
Device and process characterisation, device parameter extraction schemes
Mathematics of circuits and systems theory
Test and measurement techniques involving electronic circuits, circuits for industrial applications, sensors and transducers