Iet Circuits Devices & Systems最新文献

Typical resonant converter controllers are based on linearised averaged models, which have significant modelling errors when there are wide fluctuations in the input voltage, load and reference voltages. In this article, a piecewise affine (PWA) switching surface with active border tuning of affine sections, called the Partition Border Tuning (PBT) controller, is proposed for DC–DC series resonant converters (SRCs). Lyapunov stability analysis is used to ensure closed-loop stability. A new Chattering Mitigation (CM) technique is proposed to suppress unwanted oscillations between modes and output voltage overshoot under transient conditions, which are generally present in conventional switching surface controllers. This technique eliminates chattering, reduces output voltage overshoot and limits the maximum inductor current and capacitor voltage amplitude of the resonant tank under transient conditions. Simulation and experimental data are presented to demonstrate the effectiveness of the proposed approach.

Aiming at the modeling problem of bipolar distributed photovoltaic (DPV) cluster, this paper proposes a clustering equivalent modeling method based on clustering algorithm. First, by analyzing the detailed model of bipolar DPV, it is found that the indexes that can reflect its steady-state and dynamic characteristics mainly include energy storage element parameters such as inductance and capacitance and PI control parameters. Then, combined with the five commonly used clustering algorithms, the clusters composed of ten DPVs are clustered and grouped. Finally, the dynamic simplified model of DPV cluster is obtained by parameter aggregation and model equivalence of DPV in the same group. The above analysis is simulated and verified on the IEEE33 node system containing 10 DPVs, and the traditional single-machine equivalent model and double-machine equivalent model and clustering model are added for comparative analysis. The simulation results show that the clustering equivalent model can correctly reflect the dynamic response characteristics of DPV clusters under different working conditions. The error between each clustering model and the detailed model is not more than 10%. Among them, the fuzzy C-mean (FCM) clustering model has the best effect, the minimum error is 0.11%, and the maximum error of the single machine equivalent model is 9.3%.

Both circuit performance and long-term reliability are significantly impacted by the combined effects of temperature-induced drive current fluctuations and self-heating in FinFET devices. The performance of a three-stage rail-to-rail dynamic comparator based on a 7 nm FinFET is examined in this work, taking into account the effects of thermal changes caused by supply voltage and input voltage (ΔV_in) as well as bias temperature instability (BTI) stress. When compared to traditional bulk CMOS comparators, FinFET-based three-stage rail-to-rail dynamic comparators show essentially different delay–temperature characteristics, according to extensive HSPICE simulations. Even in the super-threshold supply voltage domain, the 7 nm FinFET-based design shows decreased delay but increased power consumption as temperature rises, in contrast to CMOS comparators, where delay usually increases with temperature. However, at high temperatures, leakage power dissipation increases dramatically, resulting in a loss of performance. With immediate applications in ultralow-power Internet of Things (IoT) nodes, sophisticated memory sense amplifiers, high-frequency communication systems, and portable biomedical equipment, these insights are especially helpful in directing the design of next-generation high-speed and energy-efficient mixed-signal circuits.

This paper presents the design of an integrated wideband active coupler, using a universal structure designed for 45° and 180°, to realize arbitrary phase shifts below 90° and above 90°, respectively, by adjusting a pair of capacitors in the coupler. Furthermore, continuous phase shifts within the ranges of 180°–135° and 40°–90° are achieved. The variable capacitor in the passive network (PN) is implemented using variable capacitance, implemented by a transistor and by adjusting dimensions and gate-source biasing. Each PN in the coupler is configured as a fifth-order low-pass filter, designed by transfer matrix analysis. A systematic design procedure based on this analysis is introduced, illustrating the combination of staggering technique, lumped-element compensation, and multisection impedance transformation to provide low output phase error and improved directivity. Measurements conducted on fabricated chips in GaAs technology for the 180° (45°) coupler within the frequency range of 10–20 GHz reveal an output phase of 180° ± 1.5° (45° ± 1°), return loss better than 15 dB (15 dB), directivity greater than 30 dB (35 dB), and a coupling gain at the center frequency equal to 6 dB (5.2 dB). Continuously tunable output phase couplers for the phase ranges of 40°–90° and 180°–135° are achieved, based on the proposed universal structure, for each 2 GHz bandwidth in 12–14 GHz band. Within this frequency range, impedance matching around –10 dB and phase error of ± 1° are obtained. Comparable performance is observed in each 1 GHz sub-band within the 14–20 GHz range. Additionally, simulation of the above couplers in 180 nm CMOS technology domonstrates similar performance.

Due to process deviations (Devs) in Micro LEDs, the luminous efficiency of each individual Micro LED can differ. Consequently, this leads to uneven luminance across the Micro LED matrix panel. In this study, a correction algorithm is proposed with the aim of improving luminance inhomogeneity on the panel. The brightness value of each pixel point on the LED panel is measured using a camera. Since the panel’s position may shift during detection, our approach incorporates self-detection and position correction to handle such misalignments. This eliminates the need for manually aligning the LED module to a fixed position on mechanical fixtures in our calibration system. The embedded system uses a camera to detect panel brightness and then generates correction coefficients for individual LED. Afterward, the coefficients are loaded into the FPGA control board and stored in memory as a Look-Up Table (LUT). Pixel correction on the Micro LED panel is achieved by selecting the corresponding coefficient from the LUT for each pixel position. The same procedures are iteratively performed ~3–4 times, using recursive processing to achieve superior uniformity across the Micro LED panel.

Approximate computing (AC)-based arithmetic circuits have not been reliable in sensitive applications like difference detection of bioimages. This article declares that the challenge is not established constantly. Accordingly, a new AC-based compressor with 16 transistors based on compound gates is proposed. The cell is implemented by complementary metal–oxide-semiconductor (CMOS) technology, and a novel approximate sum of absolute differences (SADs) unit is proposed using the compressor. Also, an error-correction module (ECM) is presented to improve the accuracy and error reduction of approximate SAD. The circuit performance and the accuracy of the output image after embedding the compressor in SAD are extracted, and the results show the superiority of the proposed circuits. The acceptable accuracy and performance of the SAD are proven versus standard and bioimages. In comparison with the exact type, the represented approximate 4:2 compressor reduces the power and power-delay-product (PDP) by 80% and 96%, respectively, while the utilization of the proposed compressor in SAD decreases the average power by 35% and reduces 43% of the average PDP. The quality and accuracy of the figure of merits (FoMs) support the main idea of this study for a new generation of AC-based circuits that are applicable in bioimage processing.

This paper presents a new method for direct sampling of the backscattered signal in ultrawideband (UWB) impulse radar for vital sign detection. One of the standard methods for direct sampling in UWB radars is the time-interleaving technique. In these converters, NOT gates (logical inverter gates) and tunable delay cells are typically used to create time delays and generate delayed replicas of the sampling clock. However, the challenge arises from the nonuniform delay associated with these gates and dependency on the process, voltage, and temperature (PVT), which affects the converter spurious-free dynamic range (SFDR). This paper employs a new structure using a ring counter to overcome this issue. As a result, a stable and PVT-independent sampling clock is obtained without significant overhead, compared to the conventional inverter-based delay cells approach. The proposed flip-flop-based ring counter architecture eliminates the need for analog delay tuning, offering a fully digital, PVT-resilient solution for uniform sampling in high-speed radar systems. The proposed structure has been utilized to design a 12-channel, six-bit time-interleaved swept-threshold analog to digital converter (ADC). The ADC has been in 65 nm complementary metal-oxide-semiconductor (CMOS) technology and simulated using the foundry design kit. Postlayout simulation results demonstrate a total power consumption of 28.54 mW with a 16.66 GS/s sampling rate.

The carry select adder (CSA) is a highly efficient arithmetic component commonly utilized in digital systems due to its superior speed performance. In the context of energy-efficient computing and fault-tolerant quantum computing, reversible logic emerges as a critical technology owing to its potential to reduce energy dissipation by retaining information. This article introduces an efficient design for a reversible carry select adder (ERCSA), constructed using fundamental lossless logic gates such as modified TSG (MTSG), Peres, and Fredkin Gate (FRG). The proposed design eliminates the need to compute the carry for the default carry input of “1.” Additionally, an optimized architecture is proposed to reduce the quantum cost of the circuit. The design achieves significant improvements by minimizing quantum cost, unused outputs, and gate count, while ensuring scalability for higher bit-width additions. A comparative analysis with existing reversible adder highlights substantial performance enhancements, including reduction in the number of gates (35.4%), garbage outputs (18.9%), ancillary inputs (25%), quantum cost (22.7%), and delay (29.5%) compared to recent designs. The proposed architecture was modeled in Verilog and synthesized using Xilinx Vivado Design Suite targeting the Xilinx Artix-7 FPGA family. The proposed 16-bit ERCA architecture achieves 10.86% lower power, 76.43% reduced delay, and 21.7% better area efficiency compared to existing methods. These improvements make it highly suitable for low-power and high-speed VLSI applications.

This article proposes a new high step-down converter which, on the input side, there are two series switches. The coupled inductors are used to decrease voltage gain, but on the output side of the proposed converter, two independent inductances are placed and act like interleaved, which cause to decrease output current ripple. Soft switching condition is provided for all semiconductors in the proposed converter. As described, considering the structure of the proposed converter, the converter has two switches, which is the minimum switch used in this structure. Also, the switches do not impose complexity to the converter in terms of control, because these switches are controlled complementary each other. In the structure of the proposed converter, the minimum semiconductor elements are used, which include two switches and three diodes; this design makes the conduction loss of the proposed converter low and achieves higher efficiency. A sample laboratory of the proposed converter is implemented to verify theoretical analysis, which the experimental results are presented in 300 W power with 320 V input voltage and 24 V output voltage. In this test, an efficiency of about 94.6% is achieved.

This study examines the influence of cell capacitance on data retention characteristics in dynamic random access memory (DRAM) cells composed of two transistors, in short, 2-transistor (2T) DRAM. The 2T DRAM is gaining attention not only as a standalone memory technology but also as a critical component for processing-in-memory (PIM) applications, offering the full compatibility with standard Si processing. The 2T configuration employs separate transistors for write and read operations, enabling flexible bit-cell design and efficient parallel processing in PIM architectures. However, the small storage node (SN) capacitance, especially when the cell capacitor is truncated, poses challenges for data retention. This work presents a design methodology to enhance data retention in 2T DRAM cells by optimizing transistor dimensions and biasing schemes. Circuit simulations using the 180 nm standard process show that the proposed approach improves retention time by 35% and reduces leakage current by 22% compared to baseline designs. Furthermore, the write transistor current demonstrates a 15% improvement in stability during repeated read operations within the retention time. These results highlight the potential of the proposed design to mitigate retention-related issues and enhance computational accuracy in PIM applications.