Arithmetic Units for RNS Moduli {2n-3} and {2n+3} Operations

P. M. Matutino, R. Chaves, L. Sousa
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引用次数: 35

Abstract

A new moduli set {2n-1, 2n+3, 2n+1, 2n-3} has recently been proposed to represent numbers in Residue Number Systems (RNS), increasing the number of channels. With this, the processing time can be reduced by simultaneously exploiting the carry-free characteristic of the modular arithmetic and improving the parallelism. In this paper, hardware structures for addition and multiplication operation in RNS for the moduli {2n-3} and {2n+3} are proposed and analyzed. In order to evaluate the performance of the proposed units they were implemented on an ASIC technology. The obtained experimental results suggest that the performance of the moduli {2n\pm3} are acceptable but demand more area resource and impose a larger delay than the typically used {2n\pm1} arithmetic units. Addition units require at least 42\% more area for a performance identical to the {2n+1} modulo adder. The multiplication units require up to 37% more area and impose a delay 25% higher. This paper also suggests that more balanced moduli sets should be developed in order to achieve more efficient RNS.
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RNS模{2n-3}和{2n+3}运算的算术单位
最近提出了一个新的模集{2n- 1,2n + 3,2n + 1,2n -3}来表示剩余数系统(RNS)中的数,从而增加了信道的数量。利用模块化算法的无携带特性,提高并行性,缩短了处理时间。本文提出并分析了模{2n-3}和模{2n+3}的RNS中加乘运算的硬件结构。为了评估所提出的单元的性能,它们在ASIC技术上实现。得到的实验结果表明,模{2n\pm3}的性能是可以接受的,但比通常使用的{2n\pm1}算术单元需要更多的面积资源和施加更大的延迟。为了获得与{2n+1}模加法器相同的性能,加法单元至少需要多42%的面积。乘法单元需要的面积增加37%,延迟增加25%。本文还提出,为了实现更高效的RNS,需要开发更多的平衡模集。
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