Techniques to increase the computational throughput of bit-serial architectures

Abstract

Three architectural techniques are reported, which accelerate bit-serial computation without compromising its favourable advantages. In essence these techniques rely on multi-wire representations of serial data - a step towards bit-parallelism. Interfacing techniques are developed to support the existence of domains of different throughput within a system, thereby enhancing the range of bandwidth-matching techniques available to the systems designer. These techniques also realise the potential to mix processing wordlengths within a serial-data system.