SeSCG: Selective sequential clock gating for ultra-low-power multimedia mobile processor design

Abstract

For ultra-low-power multimedia mobile processor (MMP) design, clock-power reduction is critical because the largest portion of the total power (more than 60% in the processor designs used in this paper) is consumed in the sequential logic. Currently, for the clock-power reduction, traditional combinational clock gating scheme has been used in industry and recently, sequential clock gating method is introduced by a few advanced CAD vendors. In order to maximize the power reduction of the MMP design, we propose a novel selective sequential clock gating (SeSCG) technique in this paper. The SeSCG scheme can choose optimal sequential clock gating style selectively for ultra-low-power design based on the proposed toggle rate analysis at RT level. We have tested the proposed technique on two real industrial MMP designs using 65 nanometer technology. The experimental results show that the conventional sequential clock gating scheme even increases average 4.77% of total power while the proposed SeSCG technique decreases average 23.71% total power with reasonably very small area overhead (no more than 0.63%) when we use real industrial testbenches for the two industrial MMP designs.