Performance estimations of gate-all-around silicon nanowire FETs with asymmetric barrier heights at source/drain

Abstract

The performance of n-channel gate-all-around silicon nanowire FETs with asymmetric barrier heights at source/drain (ASB-SiNW-FET) was simulated. Some impact factors are studied. The results suggest that the drain current and threshold voltage are mainly determined by source-side barrier height (S-SBH). Increasing S-SBH or decreasing nanowire radius can optimize sub-threshold slope, while decreasing S-SBH can enhance the drain current and suppress the fluctuation of threshold voltage.