Simulation and measurement for decoupling on multilayer PCB DC power buses

Abstract

DC power bus decoupling of a multi-layer PCB is modeled by a combination of a lumped circuit model at low frequencies (<200 MHz), and a mixed-potential integral equation approach at high frequencies. In order to determine the lumped parameters of via interconnects, an effective procedure using a network analyzer has been developed to characterize the trace/via inductances/resistances. For an 8"/spl times/10" ten-layer test board used in this study, the simulations show good agreement with the measurement. This method can lead to new design strategies of decoupling for multilayer PCB power buses.