Advanced channel and contact technologies for future CMOS devices

Abstract

Technology options for reducing channel and contact resistances in advanced transistors will be reviewed. Strain engineering techniques for enhancing electron and hole mobilities will be discussed, e.g. novel source/drain (S/D) stressors, buried stressors, novel high stress liners, etc. Also, external series resistance Rext has become a more dominant component of the total resistance between S/D in recent years. Solutions for reducing RC will be discussed. Approaches to reduce electron and hole barrier heights between the metallic contact and S/D region will be discussed.