Processing N-ary trees in reconfigurable hardware

Abstract

The paper discusses effectiveness of N-ary trees for solving different application problems with case studies on search and sort. A new method for representation of trees in memory, which takes advantages of widely available in commercial Field-Programmable Gate Array (FPGA) built-in block RAM, is proposed. It is shown that N-ary trees can be coded in such a way that enables the required size of memory to be significantly reduced with practically the same performance as in the previously developed methods. Thus, larger trees can be stored and further handled in FPGAs with equal hardware resources. It is also shown that the trees can be processed using both iterative and recursive techniques. The latter is discussed in detail due to opportunities for more compact and clear specifications, and comparison is done with the previous results permitting very good performance to be achieved.