Pub Date : 2015-08-27DOI: 10.1007/978-3-319-22035-2_2
K. Salah, Mohamed Abdelsalam
{"title":"IP cores design from specifications to production: Modeling, verification, optimization, and protection","authors":"K. Salah, Mohamed Abdelsalam","doi":"10.1007/978-3-319-22035-2_2","DOIUrl":"https://doi.org/10.1007/978-3-319-22035-2_2","url":null,"abstract":"","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126713556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-15DOI: 10.1109/ICM.2013.6735008
Mostafa Rizk, A. Baghdadi, M. Jézéquel, Y. Mohanna, Y. Atat
In digital communication applications, floating-point arithmetic is generally used to conduct performance evaluation studies of new proposed algorithms. This is typically limited to theoretical performance evaluation in terms of communication quality and error rates. For a practical implementation perspective, using fixed-point arithmetic instead of floating-point reduces significantly the costs in terms of area occupation and energy consumption. However, this implies a complex conversion process, particularly if the considered algorithm includes complex arithmetic operations with high accuracy requirements and if the target system presents many configuration parameters. In this context, the purpose of the paper is to investigate the influence on error rate performance related to the implementation of minimum mean-squared error (MMSE) linear turbo-equalization algorithm for multiple-input multiple-output (MIMO) systems utilizing fixed-point rather than floating-point arithmetic.
{"title":"Quantization and fixed-point arithmetic for MIMO MMSE-IC linear turbo-equalization","authors":"Mostafa Rizk, A. Baghdadi, M. Jézéquel, Y. Mohanna, Y. Atat","doi":"10.1109/ICM.2013.6735008","DOIUrl":"https://doi.org/10.1109/ICM.2013.6735008","url":null,"abstract":"In digital communication applications, floating-point arithmetic is generally used to conduct performance evaluation studies of new proposed algorithms. This is typically limited to theoretical performance evaluation in terms of communication quality and error rates. For a practical implementation perspective, using fixed-point arithmetic instead of floating-point reduces significantly the costs in terms of area occupation and energy consumption. However, this implies a complex conversion process, particularly if the considered algorithm includes complex arithmetic operations with high accuracy requirements and if the target system presents many configuration parameters. In this context, the purpose of the paper is to investigate the influence on error rate performance related to the implementation of minimum mean-squared error (MMSE) linear turbo-equalization algorithm for multiple-input multiple-output (MIMO) systems utilizing fixed-point rather than floating-point arithmetic.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116250856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-15DOI: 10.1109/ICM.2013.6734990
Haidar Taki, M. Hamze, A. Hamie, A. Sharaiha, A. Alaeddine, P. Morel, M. Guegan
In comparison with conventional SOA intensity modulators in IMDD PON systems, two cascaded SOAs can considerably improve the transmission performance of Adaptively Modulated Optical OFDM signals for low input powers, broaden the optimum operating condition ranges, and allow achieving signal bit rates of >30Gb/s over >60km SMFs.
{"title":"Adaptively Modulated Optical OFDM transmission using two cascaded SOAs for optical access networks","authors":"Haidar Taki, M. Hamze, A. Hamie, A. Sharaiha, A. Alaeddine, P. Morel, M. Guegan","doi":"10.1109/ICM.2013.6734990","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734990","url":null,"abstract":"In comparison with conventional SOA intensity modulators in IMDD PON systems, two cascaded SOAs can considerably improve the transmission performance of Adaptively Modulated Optical OFDM signals for low input powers, broaden the optimum operating condition ranges, and allow achieving signal bit rates of >30Gb/s over >60km SMFs.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115296068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734947
K. Salah, Mohamed Abdelsalam
Although FPGAs are a flexible alternative to ASICs, they suffer from interconnection delay which results in comparatively poor performance. Using 3D-FPGA instead of 2D-FPGA reduces the Manhattan distance between the components which results in reduction in interconnect length, delay and hence improved performance and speed. In this paper, we introduce the recent trends in 3D FPGA architectures, discuss the challenges, and display the performance evaluation metrics.
{"title":"Emerging reconfigurable systems: Exploring 3D FPGA architectures","authors":"K. Salah, Mohamed Abdelsalam","doi":"10.1109/ICM.2013.6734947","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734947","url":null,"abstract":"Although FPGAs are a flexible alternative to ASICs, they suffer from interconnection delay which results in comparatively poor performance. Using 3D-FPGA instead of 2D-FPGA reduces the Manhattan distance between the components which results in reduction in interconnect length, delay and hence improved performance and speed. In this paper, we introduce the recent trends in 3D FPGA architectures, discuss the challenges, and display the performance evaluation metrics.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126005911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734959
A. Soltan, A. Radwan, A. Soliman
This paper studies the fractional order two integrator loop based sinusoidal oscillators with two fractional order elements of different orders. Two general cases have been discussed and closed forms for the oscillation frequency and oscillation condition are driven. In addition, the effect of the fractional orders on the phase difference between the two oscillatory outputs is also presented. Design procedure for the two general cases is illustrated with numerical examples and validated through circuit simulations for three examples of oscillators based on two integrator loops.
{"title":"General procedure for two integrator loops fractional order oscillators with controlled phase difference","authors":"A. Soltan, A. Radwan, A. Soliman","doi":"10.1109/ICM.2013.6734959","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734959","url":null,"abstract":"This paper studies the fractional order two integrator loop based sinusoidal oscillators with two fractional order elements of different orders. Two general cases have been discussed and closed forms for the oscillation frequency and oscillation condition are driven. In addition, the effect of the fractional orders on the phase difference between the two oscillatory outputs is also presented. Design procedure for the two general cases is illustrated with numerical examples and validated through circuit simulations for three examples of oscillators based on two integrator loops.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116043267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734997
Adnan Zein, Ghassan Bazzoun
This paper examines the cost-effectiveness of photovoltaic (PV) generator integration into existing Diesel powered mini-grids without battery storage. The case study of a 54kWp PV generator introduction at the Lebanese village of Deir-Kanoun is detailed using load and fuel consumption measurements, the design of a photovoltaic system, a thorough assessment of possible fuel savings and its financial attractiveness. It demonstrates that PV-diesel hybrid systems can be introduced with good financial benefits in the specific Lebanese situation.
{"title":"Integration of photovoltaic generators into existing diesel mini-grids in Lebanon","authors":"Adnan Zein, Ghassan Bazzoun","doi":"10.1109/ICM.2013.6734997","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734997","url":null,"abstract":"This paper examines the cost-effectiveness of photovoltaic (PV) generator integration into existing Diesel powered mini-grids without battery storage. The case study of a 54kWp PV generator introduction at the Lebanese village of Deir-Kanoun is detailed using load and fuel consumption measurements, the design of a photovoltaic system, a thorough assessment of possible fuel savings and its financial attractiveness. It demonstrates that PV-diesel hybrid systems can be introduced with good financial benefits in the specific Lebanese situation.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117037825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734977
M. Ramadan, M. Khaled, Mostafa Gad El Rab, F. Hachem, F. Harambat
In the present work, a two-dimensional code is developed to calculate the heat-exchanger thermal performance in relation to the airflow topology upstream of the heat exchanger induced by its integration in complex environments such as the car underhood compartment. It was shown that the non-uniformity in the upstream velocity distribution decreases the thermal performance of the heat exchanger.
{"title":"Development of two-dimensional code for heat exchanger thermal performance prediction - Effects of airflow velocity distribution","authors":"M. Ramadan, M. Khaled, Mostafa Gad El Rab, F. Hachem, F. Harambat","doi":"10.1109/ICM.2013.6734977","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734977","url":null,"abstract":"In the present work, a two-dimensional code is developed to calculate the heat-exchanger thermal performance in relation to the airflow topology upstream of the heat exchanger induced by its integration in complex environments such as the car underhood compartment. It was shown that the non-uniformity in the upstream velocity distribution decreases the thermal performance of the heat exchanger.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134598405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6734999
Z. El-Bazzal, M. Nahas, M. Raad, Majd Ghareeb, A. Haj-Ali
One of the main reasons for TCP's (Transport Control Protocol) degraded performance in 802.11 wireless networks is the TCP's interpretation that the packet loss is caused by network congestion. However, in wireless networks packet loss occurs mostly due to high bit error rate, packet corruption, and link failure. TCP performance in wired/wireless networks may be substantially improved if the causes of packet loss could be identified and appropriate rectifying measures could be taken dynamically during the lifetime of a TCP session. This paper proposes an end-to-end improvement approach to the current TCP protocol by extending the used RTO (Retransmission Time Out) in such a way it allows TCP an additional waiting time for wireless errors to get fixed. This approach is validated through numerical analysis and simulations, and then compared to the current implemented TCP protocol. The simulation results have demonstrated higher TCP performance in terms of traffic sent, and retransmission attempts. This is highly recommended for a wide range of applications in mixed wired and wireless scenarios.
{"title":"Improving the performance of Transport Control Protocol over 802.11 wireless networks","authors":"Z. El-Bazzal, M. Nahas, M. Raad, Majd Ghareeb, A. Haj-Ali","doi":"10.1109/ICM.2013.6734999","DOIUrl":"https://doi.org/10.1109/ICM.2013.6734999","url":null,"abstract":"One of the main reasons for TCP's (Transport Control Protocol) degraded performance in 802.11 wireless networks is the TCP's interpretation that the packet loss is caused by network congestion. However, in wireless networks packet loss occurs mostly due to high bit error rate, packet corruption, and link failure. TCP performance in wired/wireless networks may be substantially improved if the causes of packet loss could be identified and appropriate rectifying measures could be taken dynamically during the lifetime of a TCP session. This paper proposes an end-to-end improvement approach to the current TCP protocol by extending the used RTO (Retransmission Time Out) in such a way it allows TCP an additional waiting time for wireless errors to get fixed. This approach is validated through numerical analysis and simulations, and then compared to the current implemented TCP protocol. The simulation results have demonstrated higher TCP performance in terms of traffic sent, and retransmission attempts. This is highly recommended for a wide range of applications in mixed wired and wireless scenarios.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"207 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130877813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6735000
A. Serhan, E. Lauga-Larroze, J. Fournier
This paper presents a V-Band Bi-CMOS 55nm power detector designed to be used in mmWave circuits for automatic level control (ALC) and built-in self test (BIST). The proposed detector shows a simulated detection range of about 35 dB in the 50 GHz to 90 GHz frequency band. Sensitivity to -30 dBm input power is demonstrated thanks to the use of common base bipolar transistor as input stage. The design and optimization steps are described in order to provide a general methodology to design high performance power detectors.
{"title":"A V-Band BiCMOS power detector for millimeter-wave applications","authors":"A. Serhan, E. Lauga-Larroze, J. Fournier","doi":"10.1109/ICM.2013.6735000","DOIUrl":"https://doi.org/10.1109/ICM.2013.6735000","url":null,"abstract":"This paper presents a V-Band Bi-CMOS 55nm power detector designed to be used in mmWave circuits for automatic level control (ALC) and built-in self test (BIST). The proposed detector shows a simulated detection range of about 35 dB in the 50 GHz to 90 GHz frequency band. Sensitivity to -30 dBm input power is demonstrated thanks to the use of common base bipolar transistor as input stage. The design and optimization steps are described in order to provide a general methodology to design high performance power detectors.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115128975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/ICM.2013.6735023
A. Benhaoues, C. Tanougast, H. Mayache, S. Toumi, A. Dandache
Nowadays, the current challenge in the wireless digital systems is to design new digital, generic and “universal” architectures, take charge of functionalities previously managed by different circuits. Moreover, these ones must be sufficiently flexible to support multiple transmission standards and easily adaptable for future evolutions. In this work, we propose a digital architecture for modulation and demodulation using LFSR registers. The architecture was implemented on Xilinx Virtex series field programmable gate arrays (FPGA). The implementations demonstrate that our proposed architecture can deliver a high reduction of the FPGA logic requirements and consumption power when compared with the Velcro architecture.
{"title":"Digital synthesis architecture for modulation and demodulation","authors":"A. Benhaoues, C. Tanougast, H. Mayache, S. Toumi, A. Dandache","doi":"10.1109/ICM.2013.6735023","DOIUrl":"https://doi.org/10.1109/ICM.2013.6735023","url":null,"abstract":"Nowadays, the current challenge in the wireless digital systems is to design new digital, generic and “universal” architectures, take charge of functionalities previously managed by different circuits. Moreover, these ones must be sufficiently flexible to support multiple transmission standards and easily adaptable for future evolutions. In this work, we propose a digital architecture for modulation and demodulation using LFSR registers. The architecture was implemented on Xilinx Virtex series field programmable gate arrays (FPGA). The implementations demonstrate that our proposed architecture can deliver a high reduction of the FPGA logic requirements and consumption power when compared with the Velcro architecture.","PeriodicalId":372346,"journal":{"name":"2013 25th International Conference on Microelectronics (ICM)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114542317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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