Energy aware and reliable STT-RAM based cache design for 3D embedded chip-multiprocessors

Abstract

In Nano-scale technologies, static power consumption due to leakage current has become a serious issue in the design of SRAM based on-chip cache memories. To address this issue, non-volatile memory technologies such as STT-RAM (Spin Transfer Torque-RAM) have been proposed as a replacement for SRAM cells due to their near zero static power consumption and high memory density. Nonetheless, STT-RAMs suffer from some failures such as read disturb and limited endurance as well as high switching energy. One effective way to decrease the STT-RAMs' switching energy is to reduce their retention time, however, reducing the retention time has a negative impact on the reliability of STT-RAM cells. In this paper, we propose a hybrid cache layer for an embedded 3D-Chip Multiprocessor which employs two types of STT-RAM memory banks with retention time of 1s and 10ms to provide a beneficial tradeoff between reliability, energy consumption, and performance. To this end, we also propose an optimization model to find the optimal configurations for these two kinds of memory banks. Simulation results using the Gem5 simulator through comparisons with fully SRAM and fully STT-RAM based cache show that the proposed hybrid cache consumes significantly less power while offering higher throughput (instructions per cycle) compared to a fully STT-RAM based cache.