{"title":"When processors get old: Evaluation of BTI and HCI effects on performance and reliability","authors":"C. Sandionigi, O. Héron, C. Bertolini, R. David","doi":"10.1109/IOLTS.2013.6604076","DOIUrl":null,"url":null,"abstract":"This paper investigates the problem of Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) on processors. We propose a performance- and reliability-aware methodology that evaluates the effects of these degradation mechanisms at design time. The performed analysis estimates the effects produced by the execution of applications, representing typical or worst case scenarios, or single instructions. As shown by the experimental results, our framework allows to estimate the performance degradation and to identify the areas of memory most subject to faults, with the objective of optimizing the system design and defining on-line strategies.","PeriodicalId":423175,"journal":{"name":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE 19th International On-Line Testing Symposium (IOLTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IOLTS.2013.6604076","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
This paper investigates the problem of Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) on processors. We propose a performance- and reliability-aware methodology that evaluates the effects of these degradation mechanisms at design time. The performed analysis estimates the effects produced by the execution of applications, representing typical or worst case scenarios, or single instructions. As shown by the experimental results, our framework allows to estimate the performance degradation and to identify the areas of memory most subject to faults, with the objective of optimizing the system design and defining on-line strategies.