{"title":"Logic cell design for on-line testable FPGAs","authors":"P. Lala, A. Singh","doi":"10.1109/APASIC.1999.824101","DOIUrl":null,"url":null,"abstract":"This paper proposes a self-checking logic cell that can be used as the building block for on-line testable FPGAs. The proposed cell consists of three 4-to-1 multiplexers, a 2-to-1 multiplexers and a D flip-flop. These multiplexers and the D flip-flop are designed using differential cascode voltage switch logic. Any single transistor fault (stuck-on/off) as well as single stuck-at faults at the inputs of the multiplexers or the D flip-flop can be detected on-line.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APASIC.1999.824101","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper proposes a self-checking logic cell that can be used as the building block for on-line testable FPGAs. The proposed cell consists of three 4-to-1 multiplexers, a 2-to-1 multiplexers and a D flip-flop. These multiplexers and the D flip-flop are designed using differential cascode voltage switch logic. Any single transistor fault (stuck-on/off) as well as single stuck-at faults at the inputs of the multiplexers or the D flip-flop can be detected on-line.