Development of a reduction algorithm for CAN frame bits

Abstract

Controller Area Network (CAN) protocol uses Cyclic Redundancy Check (CRC) code as a self-correcting scheme to detect and correct errors. Also, the assigned CRC generator polynomial for CAN is CRC-15. Therefore, no matter what is the size of the data frame to transmit, it already consumed 15 bits for CRC frame that causes to decrease the CAN's frame rate. The main objective of this paper is to use a different error correction technique which is called as the Enhanced-Error Detection (EED) code and aims to increase the CAN's frame rate. The computed redundancy bits depends on the total number of transmitted bits instead of a fixed set of bits. Moreover, these redundancy bits will be placed right after of the data bits' position like in CRC scheme. This proposed method is synthesized using Xilinx Virtex-5 FPGA. The simulation results show a significant increase of CAN's frame rate and can be a better option for detecting and correcting the error in CAN System.