Package substrate built-in three-dimensional distributed matching circuit for high-speed SerDes applications

Abstract

This paper proposes a new method to resolve the on-die capacitance issue of the high-seed SerDes (serializer-deserializer). This issue can be resolved by incorporating a three-dimensionally controlled distributed impedance matching circuit into the package substrate. The distributed matching circuit has been applied to the 6.25 Gbps SerDes device by using a conventional build-up substrate as a package substrate. As a result, the return loss showed a ~6 dB (~200%) improvement as well as showing a better signal waveform than standard 50 Ohm package design. Because this method does not require any additional manufacturing technology other than conventional build-up substrate, the cost of high speed (Gbps) communication devices can be reduced and also extend conventional technology to the even higher speed devices.