An improved design for high speed analog applications of the fully differential operational floating conveyor

Abstract

This paper presents a novel concept along with a suggested CMOS-based design of the fully differential operational floating conveyor (FD-OFC). The FD-OFC concept and design has been introduced for the first time by the authors [9] as an 8 (4×4) port general purpose analog building block. The differential action offered by the proposed design can be empolyed in numerous analog and/or hybrid (analog/digital) VLSI applications, particularly where a high noise rejection ratio is desired. Furthermore, the proposed design can operate under biasing conditions as low as 1.2 V (instead of the 1.5 V bias in [9]) at frequencies up to 600 MHz in addition to higher open loop transimpedance gain of 104 dB (compared to 44.5 dB in [9]). These operating conditions recommend the proposed device to be integrated to a wide range of low power-high speed applications. The terminal behavior of the proposed device is mathematically modeled and its operation is simulated using the UMC 130 nm technology kit in Cadence environment.