Design of low power subthreshold linear feedback shift registers

Abstract

This paper focuses on the design of linear feedback shift register (LFSR) in subthreshold regime. An LFSR requires D flip flops and exclusive OR (XOR) gates for its realization. Four different LFSR architectures based on different types of circuits for D flip flop and XOR gate are put forward. The first architecture uses true-single phase clock (TSPC) D flip-flop and static CMOS XOR gate, the second employs TSPC based D flip-flop and Transmission Gate based XOR gate. The other two architectures use transmission gate based D flip flop and differ in the use XOR gate (static CMOS or transmission gate). The functionality of the proposed architectures is verified through SPICE simulations using 0.18 µm TSMC CMOS technology parameters. The performance of the proposed architectures is compared on the basis of highest frequency and power consumption. It is found that the LFSR employing TSPC based D flip flop are capable of achieving highest operating frequency and satisfy the low-power concern of the VLSI chips.