Modified Error Tolerant Adder for Digital Signal Processing Applictaion

Abstract

The trade-off between speed and power consumption has become a critical concern as process technology make in-roads to 40nm proximity in modern VLSI technology. We can reduce this trade-off by compensating with accuracy i.e. if an application like Digital signal processing (DSP) can accept some errors then a large power can be saved and at the same time speed can be enhanced. In this paper, we propose a Modified Error Tolerant Adder (META) in 65nm CMOS process technology that will provide better performance with limited accuracy compensation.