A CMOS correlator for UWB front-end circuit

Chunjiang Tu, Boan Liu, Hongyi Chen
{"title":"A CMOS correlator for UWB front-end circuit","authors":"Chunjiang Tu, Boan Liu, Hongyi Chen","doi":"10.1109/ICASIC.2005.1611364","DOIUrl":null,"url":null,"abstract":"A CMOS analog correlator designed using SMIC/spl reg/ 0.18/spl mu/m CMOS mixed and RF technology is proposed in this paper. The correlator is mainly composed of a Gilbert cell, common mode feedback (CMFB) circuit, capacitor load and buffer. The correlator can be used in the ultra wideband (UWB) receivers.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 6th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASIC.2005.1611364","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

Abstract

A CMOS analog correlator designed using SMIC/spl reg/ 0.18/spl mu/m CMOS mixed and RF technology is proposed in this paper. The correlator is mainly composed of a Gilbert cell, common mode feedback (CMFB) circuit, capacitor load and buffer. The correlator can be used in the ultra wideband (UWB) receivers.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
一种用于超宽带前端电路的CMOS相关器
本文提出了一种采用SMIC/spl reg/ 0.18/spl μ m CMOS混合射频技术设计的CMOS模拟相关器。该相关器主要由吉尔伯特单元、共模反馈(CMFB)电路、电容负载和缓冲器组成。该相关器可用于超宽带(UWB)接收机。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
A CMOS continuous-time Gm-C filter and programmable gain amplifier for WPAN receivers A VLSI architecture for motion compensation interpolation in H.264/AVC Transition traversal coverage estimation for symbolic model checking Power reduction in high-speed inter-chip data communications An optimization of VLSI architecture for DFE used in Ethernet
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1