Improving Memory Repair by Selective Row Partitioning

Abstract

A new methodology for improving memory repair is presented which can be applied in either manufacture time repair or built-in self-repair (BISR) scenarios. In traditional memory repair, one spare column can only replace one column containing a defective cell. However, the proposed method allows a single spare column to be used to repair multiple defective cells in multiple columns. This is done by selectively decoding the row address bits when generating the control signals for the column MUXes. This logically segments the spare column allowing it to replace different columns in different partitions of the row address space. The hardware is the same for all chips, but fuses are used to customize the row decoding circuitry on a chip-by-chip basis. An algorithm is described for choosing which row address bits to decode given the defect map for a particular chip. This additional degree of freedom allows customization based on the defect map of a chip and increases the effectiveness of the proposed scheme in comparison to traditional memory repair. Experimental results show that, when compared with traditional schemes of similar complexity, the proposed scheme achieves a higher probability of repairing defects.