{"title":"A 2.4-GHz Fully CMOS Integrated Transmitter for 802.1lb Wireless LAN","authors":"Jirou He, Xiaoping Gao, Weilun Shen, Xiaofeng Yi, Yumei Huang, Zhiliang Hong","doi":"10.1109/ICASIC.2005.1611330","DOIUrl":null,"url":null,"abstract":"Featuring a direct-conversion architecture, a 2.4-GHz radio-frequency (RF) transmitter frontend for 802.11b wireless LAN (WLAN) is implemented in 0.18-mum CMOS technology. Direct-conversion architecture minimizes the on-and-off-chip components required and provides a low-cost and low-power solution. The transmitter incorporates two low-pass filters (LPFs), a single-sideband (SSB) mixer, a power amplifier driver and a divide-by-two circuit for quadrature LO generation. The transmitter provides a gain control of 12 dB in 3-dB steps and an output 1-dB compression of 7.7 dBm while delivering a nominal output power of 0 dBm. The chip consumes 40 mA from a 1.8-V supply and occupies an area of 2.5 times 2 mm2 including pads","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 6th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASIC.2005.1611330","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Featuring a direct-conversion architecture, a 2.4-GHz radio-frequency (RF) transmitter frontend for 802.11b wireless LAN (WLAN) is implemented in 0.18-mum CMOS technology. Direct-conversion architecture minimizes the on-and-off-chip components required and provides a low-cost and low-power solution. The transmitter incorporates two low-pass filters (LPFs), a single-sideband (SSB) mixer, a power amplifier driver and a divide-by-two circuit for quadrature LO generation. The transmitter provides a gain control of 12 dB in 3-dB steps and an output 1-dB compression of 7.7 dBm while delivering a nominal output power of 0 dBm. The chip consumes 40 mA from a 1.8-V supply and occupies an area of 2.5 times 2 mm2 including pads