{"title":"A 52 GHz VCO with low phase noise implemented in SiGe BiCMOS technology","authors":"L. Jia, A. Cabuk, Jianguo Ma, K. Yeo","doi":"10.1109/IWSOC.2003.1213046","DOIUrl":null,"url":null,"abstract":"A fully integrated 52 GHz millimeter wave LC VCO with -106 dBc/Hz phase noise at 600 kHz offset frequency and 0.93 GHz tuning range is reported in the paper using IBM BiCMOS-6HP technology. The output voltage swing of the VCO is about 0.4 Vp-p for the complementary cross-coupled topology with the buffer. A bipolar device is used as the tail transistor to supply constant a current to preserve the oscillation of the VCO. The parasitics due to interconnect metals are extracted from the layouts, the effects of those parasitics on the VCO's performance are investigated. Based on the analyses, the optimized layout of the complementary VCO is obtained, the pre-layout and the post-layout simulations are compared and presented in this paper.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWSOC.2003.1213046","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
A fully integrated 52 GHz millimeter wave LC VCO with -106 dBc/Hz phase noise at 600 kHz offset frequency and 0.93 GHz tuning range is reported in the paper using IBM BiCMOS-6HP technology. The output voltage swing of the VCO is about 0.4 Vp-p for the complementary cross-coupled topology with the buffer. A bipolar device is used as the tail transistor to supply constant a current to preserve the oscillation of the VCO. The parasitics due to interconnect metals are extracted from the layouts, the effects of those parasitics on the VCO's performance are investigated. Based on the analyses, the optimized layout of the complementary VCO is obtained, the pre-layout and the post-layout simulations are compared and presented in this paper.
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