ATLAS I: building block for ATM networks with credit-based flow control

Abstract

ATLAS I is a single-chip, high-performance ATM switch that implements an innovative, advanced ar chitecture with optional multilane (per VC) credit based (backpressure) flow control for data (e.g., ABR) traffic, while allowing use of rate-based flow control wherever desired. The chip is being developed as a next generation gigabit ATM switch under ACTS project "ASICCOM" of the European Union. We describe the architecture of ATLAS I with emphasis on its use as a building block for universal high-speed networking, i.e. for use as a general purpose ATM switch core for the wide, local, and system area. Its single-chip fabrication targets low cost, which will enable wider deployment of ATM technology in all areas of interconnection. Adoption of the optional credit-based flow control can result inefficient, high-speed data networks, that provide improved performance characteristics when compared to wormhole networks. We present simulation re sults indicating that ATLAS I based networks can provide significantly improved delay and through put characteristics over wormhole networks, especiatly under bursty and hot-spot traffic, which is very common in distributed and parallel processing applications.