A Dynamic Current-offset Calibration (dcc) Sense Amplifier With Fish-bone Shaped Bitline (fbb) For High-density Srams

Abstract

I n t r o d u c t i o n As the density of SRAM increases, a large number of block division has been required. As each block has its own pcriphcral circuits such as decoder and sense amplifier. the die size of the SRAM increases proportional to the number of the blocks. Reducing the number of local decoders is one answer to the problem. In this viewpoint, the SCPA architecture has becn proposed[l]. So the remaining problem is how to decrease the number of sense amplifiers. Since one sense amplifier is connected to a long bitline pair, two new problems appear. One is increased bitline capacitance, the other is a large bitline parasitic resistance. Both issues inevitably increase the sensing delay. Moreover, the offset caused by mismatch of devices also incrcases the sensing delay. In following sections, these problems are solved by using DCC and FBB. The DCC can improve the sensing delay by dynamically cancelling the current offset. Combining FBB and DCC, the problems of increased bitline rcsistance c m be solved. These effects of each scheme are explained by applying these technique to 16Mbit SRAM.