Analog performance of submicron GC SOI MOSFETs

Abstract

This paper aims to demonstrate the performance of GC SOI MOSFET devices in comparison to standard SOI MOS transistors, comparing the improvements achieved by the adoption of the GC architecture in a submicron fully depleted SOI technology varying the channel length. The results obtained by two-dimensional numerical simulations show that the best improvement is obtained when the length of lightly doped region length is approximately 100 nm, independently of the total channel length.