{"title":"Compact Modeling of Flicker Noise in High Voltage MOSFETs and Experimental Validation","authors":"R. Goel, Y. Chauhan","doi":"10.1109/LAEDC51812.2021.9437922","DOIUrl":null,"url":null,"abstract":"An analytical model of flicker noise (also called 1/f or low frequency noise) for the drift region is developed to formulate a 1/f model for high voltage MOSFETs using the sub-circuit approach in this work. For halo doped drain extended MOSFET (DEMOS), the contribution factors of halo, channel and drift regions are obtained to capture anomalous behavior of 1/f noise. Similar to Halo doped DEMOS, for LDMOS, the contribution factors for channel and the drift region are obtained to capture the SID for different drain biases and channel lengths. The proposed model is validated with measurement data of 50V LDMOS and DEMOS.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"198 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LAEDC51812.2021.9437922","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
An analytical model of flicker noise (also called 1/f or low frequency noise) for the drift region is developed to formulate a 1/f model for high voltage MOSFETs using the sub-circuit approach in this work. For halo doped drain extended MOSFET (DEMOS), the contribution factors of halo, channel and drift regions are obtained to capture anomalous behavior of 1/f noise. Similar to Halo doped DEMOS, for LDMOS, the contribution factors for channel and the drift region are obtained to capture the SID for different drain biases and channel lengths. The proposed model is validated with measurement data of 50V LDMOS and DEMOS.