Channel engineering towards a full low temperature process solution for the 45 nm technology node [NMOS transistors]

Abstract

This work analyses the impact of junctions formed by solid phase epitaxial re-growth (SPER) on the electrical characteristics of NMOS transistors. These ultra shallow junctions allow us to control the short channel effects (SCE) and to improve the transistor performance down to 30 nm channel lengths. We demonstrate the viability of an ultra low temperature process, enabling the activation of B halo and S/D junction dopant. We also show that the junction leakage can be reduced with the SPER process, compared with the standard spike anneal junction.