{"title":"Cramer-Rao analysis of reduced order STAP processors","authors":"R. Klemm","doi":"10.1109/RADAR.2000.851899","DOIUrl":null,"url":null,"abstract":"The Cramer-Rao bounds (CRB) of azimuth and velocity estimates of suboptimum space-time adaptive (STAP) processors are presented. Several spatial and space-time order reducing transforms are analysed and compared with the optimum (ML) processor. Although some of the processors discussed exhibit near-optimum performance in terms of signal-to-clutter ratio some of them produce high standard deviations of target velocity and azimuth. Since estimation errors are a major input of subsequent tracking algorithms the selection and design of an appropriate processor architecture is an important task.","PeriodicalId":286281,"journal":{"name":"Record of the IEEE 2000 International Radar Conference [Cat. No. 00CH37037]","volume":"288 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Record of the IEEE 2000 International Radar Conference [Cat. No. 00CH37037]","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RADAR.2000.851899","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
The Cramer-Rao bounds (CRB) of azimuth and velocity estimates of suboptimum space-time adaptive (STAP) processors are presented. Several spatial and space-time order reducing transforms are analysed and compared with the optimum (ML) processor. Although some of the processors discussed exhibit near-optimum performance in terms of signal-to-clutter ratio some of them produce high standard deviations of target velocity and azimuth. Since estimation errors are a major input of subsequent tracking algorithms the selection and design of an appropriate processor architecture is an important task.