{"title":"Design and optimization of narrow band low noise amplifier using 0.18µm CMOS","authors":"Hasmukh P. Koringa, V. Shah","doi":"10.1109/ICCN.2015.21","DOIUrl":null,"url":null,"abstract":"In this paper, an optimized design procedure based on evolutionary algorithms for automatic synthesis of a current reuse cascode fully integrated low noise amplifiers (LNA) targeted @2.4GHz is discussed. Here genetic Algorithm is intended to compute the circuit elements values and bias levels capable of maintaining the best level of gain, input matching, and power consumption. The circuit simulate using 0.18μm RF CMOS TSMC technology for to evaluate performance. Automatic circuit design using evolutionary optimization algorithm optimized design taking less computation time compare to tremendous manual trial. The Simulation results show the power gain (S21) and input matching (S11) are 26dB and -13dB respectively @2.4GHz. Simulation results demonstrate output reflection (S12) is less than -35dB and current sink form 1.8V supply is only 5.6mA.","PeriodicalId":431743,"journal":{"name":"2015 International Conference on Communication Networks (ICCN)","volume":" 6","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 International Conference on Communication Networks (ICCN)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCN.2015.21","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
In this paper, an optimized design procedure based on evolutionary algorithms for automatic synthesis of a current reuse cascode fully integrated low noise amplifiers (LNA) targeted @2.4GHz is discussed. Here genetic Algorithm is intended to compute the circuit elements values and bias levels capable of maintaining the best level of gain, input matching, and power consumption. The circuit simulate using 0.18μm RF CMOS TSMC technology for to evaluate performance. Automatic circuit design using evolutionary optimization algorithm optimized design taking less computation time compare to tremendous manual trial. The Simulation results show the power gain (S21) and input matching (S11) are 26dB and -13dB respectively @2.4GHz. Simulation results demonstrate output reflection (S12) is less than -35dB and current sink form 1.8V supply is only 5.6mA.