Device design for sub 90 nm MOSFETs for sample and hold circuits

Abstract

In this paper, we have extensively studied how different device parameters affect the constituents of sampling circuit performance metrics. As the MOSFET is scaled into the sub-90 nm regime, for ADCs using moderate sampling rate and high resolutions, the gate tunneling current not only severely degrades the droop rate but also affects the nonlinearity adversely. The effect of scaling on various trade-offs that exist among the metric constituents is also presented. These device guidelines can be used to improve the sample and hold operation to a fairly general degree.