Methodology for early and accurate test power estimation at RTL

Abstract

Test power consumption impacts various aspects of an SOC design cycle ranging from packaging and power grid design to tester power supply requirements. Obtaining early and accurate test power estimates has so far been a bottleneck since design-for-test (DFT) modifications such as scan manifest only in the gate-level circuit representation. In this work, we describe a methodology that enables us to perform early and efficient power estimation for scan-based circuits at RTL. We explain the method, its realization using features of a commercial power estimation engine and its evaluation on various production 65nm and 45nm industrial designs.