A Class of Recursive Networks on a Chip for Enhancing Intercluster Parallelism

Abstract

Future VLSI technologies will allow for multiple clusters each of a number of processing nodes to be put on a single chip. Although we may then be able to select a network topology matching an application assigned to each cluster, it may be difficult to decide the topologies of connections between the (intra)cluster networks for effective parallel processing by the cooperation of clusters. To alleviate the problem, this paper proposes a class of recursive networks, RNs, of which constituent networks can have different topologies and sizes in different recursive levels but also in the same level. In RN, the last-level networks define the cluster networks, and the level-i network associated with a cluster network defines the i-th intercluster network between the cluster and another cluster. The cluster and intercluster networks can be any kinds of standard networks, such as the mesh and bus. The paper presents a partition-based method of generating RN and its routing and layout methods.