Baekseok Ko, Joo-Won Kim, Jaemin Ryoo, C. Hwang, Seung-Baek Park, Soo-Won Kim
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引用次数: 2
Abstract
This paper introduces a practical methodology to improve power integrity performance of the chip-package-PCB systems for smart TVs. For power integrity analysis, a chip, package and PCB are modeled as lumped element circuits for simplicity. Case studies are presented to optimize MLCC placement using chip-package-PCB co-simulation under fixed SoC design. In case studies, CPU power net of an application processor is chosen, and voltage droop is measured as a design weight on each physical domains. The introduced methodology is evaluated through experimental verifications.
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