Modeling and Analysis a of On-Die Decoupling Capacitance in the Power Delivery Network of an Integrated Chip

Abstract

In this work, we propose an analytical approach for accurate estimation on on-die decoupling capacitance in the power delivery network (PDN) of an integrated chip (IC). This paper suggests a simplified model of PDN which avoids the complex mesh structures traditionally generated but still provides a good fit model with measurement. The suggested model consists of branched multiple cells in a chained node formation. By manipulating multiple variables accounting for a complex PDN structure, the curve fitting process was performed and the best-fitted curve was found to be valid with less than 3% error tolerance through the solution-search processes by comparing capacitor values in a known mesh structure. Consequently, complex matrix PDN can be simplified and converted to an analytical model through the proposed chained structure. This approach is expected to effectively validate the value of implemented decoupling capacitance in the PDN of a designed IC with conventional low-impedance measurement techniques.