Sub- 0.18μm low leakage and high performance dynamic logic wide fan-in gates

Abstract

MOSFET scaling affects the leakage and delay of VLSI circuits. Moreover implementation of wide fan in gates increases leakage and delay. This paper shows the comparative analysis of power and delay of various domino logic which are implemented in wide fan-in gates. The effect on delay due to the variations in various factors such as supply voltage, temperature and signal strength has been presented. There are two kinds of delay that have been considered: D-Q delay and C-Q delay This will give a better understanding about different dynamic gates and make the decisions for designing high performance, low leakage and sizing of VLSI systems. The schematic entry as well as the simulations were done using Mentor Graphics tool kit. The circuit layout has been implemented in IC workstation and run in Calibre for physical verification using TSMC 180nm process technology at 1.8V.